1. Field of the Invention
The present invention relates to a data check circuit.
2. Description of the Related Art
A system LSI including CPU (Central Processing Unit) may be provided with a memory for storing program data of the CPU on the outside of the system LSI so as to flexibly change processing executed by the CPU, for example. In such a system, in order to facilitate the acquisition of the program data by the CPU, generally, the program data is transferred from an external memory to RAM (Random Access Memory) included in the system LSI, for example. If the program data is transferred to the RAM, the CPU executes the program data stored in the RAM so as to execute various processing.
When program data is transferred from an external memory to the internal RAM, incorrect program data may be stored in the RAM due to the effect of noise such as static electricity. Even if the program data is correctly stored in the RAM, an error may occur in the program data afterward due to the effect of noise. Therefore, the CPU is required to check whether or not an error occurs in the program data stored in the RAM, for example, on a regular basis (see, e.g., Japanese Patent Application Laid-Open Publication No. 2004-38541).
Since the CPU executes and checks the program data, the CPU is able to check the program data in such appropriate timing that a load of the CPU is small, for example. However, as the program data stored in the RAM increases in data size, a period of checking the program data generally increases. Therefore, even if the CPU starts checking the program data in appropriate timing, the load is applied in checking the program data, thereby reducing the efficiency of the processing that should originally be executed by the CPU, which is a problem.